\relax 
\citation{Tomasi1998}
\citation{zhang2008}
\citation{eisemann2004}
\citation{Bae2006}
\citation{DeCarlo2002}
\citation{Xiao2006}
\citation{Ramanath2003}
\citation{Paris2009}
\citation{Pham2005}
\citation{yang2009}
\citation{xu2009}
\citation{xu2009}
\@writefile{toc}{\contentsline {section}{\numberline {I}Introduction}{1}}
\newlabel{sec:intro}{{I}{1}}
\citation{Tomasi1998}
\@writefile{toc}{\contentsline {section}{\numberline {II}Bilateral Filtering Kernel}{2}}
\newlabel{sec:stencil}{{II}{2}}
\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces Example of a filter at the starting position of the image}}{2}}
\newlabel{fig:filter}{{1}{2}}
\newlabel{spatial}{{1}{2}}
\newlabel{photometric}{{3}{2}}
\newlabel{combined}{{5}{2}}
\newlabel{eq:depen}{{7}{2}}
\citation{Paris2009,Pham2005}
\@writefile{lof}{\contentsline {figure}{\numberline {2}{\ignorespaces Example of a naive bilateral filter iterations}}{3}}
\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {II-A}}A Naive Approach to bilateral filtering kernel}{3}}
\@writefile{loa}{\contentsline {algorithm}{\numberline {1}{\ignorespaces Naive bilateral Filter Algorithm}}{3}}
\newlabel{alg:Example-Algorithm-float}{{1}{3}}
\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {II-B}}Pair-symmetric bilateral filtering kernel}{3}}
\@writefile{toc}{\contentsline {section}{\numberline {III}CUDA-based Implementation Details}{3}}
\newlabel{sec:GPUoptimizations}{{III}{3}}
\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {III-A}}Implicit Intra-Warp Synchronization and Memory Access Patterns}{3}}
\@writefile{loa}{\contentsline {algorithm}{\numberline {2}{\ignorespaces Pair-symmetric Bilateral Filtering Algorithm}}{4}}
\newlabel{alg:Example-Algorithm-float-1}{{2}{4}}
\newlabel{fig:pspro}{{\unhbox \voidb@x \hbox {III-A}}{4}}
\newlabel{fig:pspro2}{{\unhbox \voidb@x \hbox {III-A}}{4}}
\newlabel{fig:pspro3}{{\unhbox \voidb@x \hbox {III-A}}{4}}
\@writefile{lof}{\contentsline {figure}{\numberline {3}{\ignorespaces Memory access patterns for CUDA that exploit implicit intra-warp synchronization}}{4}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(a)}{\ignorespaces {Each warp is assigned a row in filter window}}}{4}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(b)}{\ignorespaces {2 x 2 thread-blocks each with 4 x 3 threads}}}{4}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(c)}{\ignorespaces {An illustrated overview of the bilateral filtering process}}}{4}}
\newlabel{fig:intrawarp}{{3}{4}}
\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {III-B}}Shared Memory and Tile Processing}{5}}
\@writefile{lof}{\contentsline {figure}{\numberline {4}{\ignorespaces Tiling for Pair-Symmetric bilateral filtering with each tile having a unique color. Overlapping tiles have a resultant color.}}{5}}
\newlabel{fig:Tiling-for-Pair-Symmetric}{{4}{5}}
\@writefile{lof}{\contentsline {figure}{\numberline {5}{\ignorespaces Input image after one iteration of pair-symmetric algorithm. Tiles do not have perfect boundaries due to overlaps.}}{5}}
\newlabel{fig:An-iteration-of}{{5}{5}}
\@writefile{toc}{\contentsline {section}{\numberline {IV}CPU-based Implementation Details}{5}}
\newlabel{sec:optimizations}{{IV}{5}}
\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {IV-A}}Memory to computation ratio of bilateral filtering kernel}{5}}
\@writefile{lof}{\contentsline {figure}{\numberline {6}{\ignorespaces Percentage of time taken by sequential kernel when run without $exp$ instruction, $filter$ $radius$=10.}}{5}}
\newlabel{fig:noexp}{{6}{5}}
\citation{kdatta2008}
\citation{matrix-multi,MatrixMultiFloating}
\citation{NCCmatching}
\citation{Tomasi1998}
\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {IV-B}}SIMD optimizations}{6}}
\newlabel{sub:SIMD1}{{\unhbox \voidb@x \hbox {IV-B}}{6}}
\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {IV-C}}Reduction Methods}{6}}
\newlabel{sub:reduction}{{\unhbox \voidb@x \hbox {IV-C}}{6}}
\@writefile{toc}{\contentsline {section}{\numberline {V}Experimental Testbed}{6}}
\newlabel{sec:expt}{{V}{6}}
\@writefile{lot}{\contentsline {table}{\numberline {I}{\ignorespaces Architectural details of chips employed for experiments}}{7}}
\newlabel{tab:archs}{{I}{7}}
\newlabel{fig:Nehalem}{{7(a)}{7}}
\newlabel{sub@fig:Nehalem}{{(a)}{7}}
\newlabel{fig:harpertown}{{7(b)}{7}}
\newlabel{sub@fig:harpertown}{{(b)}{7}}
\newlabel{fig:corei7}{{7(c)}{7}}
\newlabel{sub@fig:corei7}{{(c)}{7}}
\@writefile{lof}{\contentsline {figure}{\numberline {7}{\ignorespaces Bilateral filtering kernel on Intel chips. The baseline version is BL\_Naive version, auto optimized by compiler with O3 and SSE flags.}}{7}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(a)}{\ignorespaces {Nehalem-EX Xeon X7650}}}{7}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(b)}{\ignorespaces {Harpertown Xeon E5410}}}{7}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(c)}{\ignorespaces {Core i7 - 870}}}{7}}
\newlabel{fig:comparisonIntel}{{7}{7}}
\@writefile{toc}{\contentsline {section}{\numberline {VI}Performance Results}{7}}
\newlabel{sec:results}{{VI}{7}}
\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {VI-A}}Performance of bilateral filtering kernel on CPU}{7}}
\newlabel{fig:barcelona}{{8(a)}{8}}
\newlabel{sub@fig:barcelona}{{(a)}{8}}
\newlabel{fig:Shanghai}{{8(b)}{8}}
\newlabel{sub@fig:Shanghai}{{(b)}{8}}
\newlabel{fig:Phenom}{{8(c)}{8}}
\newlabel{sub@fig:Phenom}{{(c)}{8}}
\@writefile{lof}{\contentsline {figure}{\numberline {8}{\ignorespaces Bilateral filtering kernel on AMD chips. The comparison is with BL\_Naive version, auto optimized by compiler with O3 and SSE flags.}}{8}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(a)}{\ignorespaces {Barcelona AMD Opteron 8350}}}{8}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(b)}{\ignorespaces {Shanghai AMD Opteron 2376}}}{8}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(c)}{\ignorespaces {AMD Phenom II 1045T}}}{8}}
\newlabel{fig:comparisonAMD}{{8}{8}}
\newlabel{fig:harpertownFinal}{{9(a)}{8}}
\newlabel{sub@fig:harpertownFinal}{{(a)}{8}}
\newlabel{fig:corei7Final}{{9(b)}{8}}
\newlabel{sub@fig:corei7Final}{{(b)}{8}}
\newlabel{fig:NehalemFinal}{{9(c)}{8}}
\newlabel{sub@fig:NehalemFinal}{{(c)}{8}}
\@writefile{lof}{\contentsline {figure}{\numberline {9}{\ignorespaces Speedup on Intel Chips using OpenMP along with SSE}}{8}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(a)}{\ignorespaces {Harpertown Xeon E5410}}}{8}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(b)}{\ignorespaces {Core i7 - 870}}}{8}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(c)}{\ignorespaces {Nehalem-EX Xeon X7650}}}{8}}
\newlabel{fig:comparisonFinalIntel}{{9}{8}}
\newlabel{fig:barcelonaFinal}{{10(a)}{8}}
\newlabel{sub@fig:barcelonaFinal}{{(a)}{8}}
\newlabel{fig:ShanghaiFinal}{{10(b)}{8}}
\newlabel{sub@fig:ShanghaiFinal}{{(b)}{8}}
\newlabel{fig:PhenomFinal}{{10(c)}{8}}
\newlabel{sub@fig:PhenomFinal}{{(c)}{8}}
\@writefile{lof}{\contentsline {figure}{\numberline {10}{\ignorespaces Speedup on AMD chips using OpenMP along with SSE}}{8}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(a)}{\ignorespaces {Barcelona AMD Opteron 8350}}}{8}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(b)}{\ignorespaces {Shanghai AMD Opteron 2376}}}{8}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(c)}{\ignorespaces {AMD Phenom II 1045T}}}{8}}
\newlabel{fig:comparisonFinalAMD}{{10}{8}}
\@writefile{lof}{\contentsline {figure}{\numberline {11}{\ignorespaces Time taken by Intel Nehalem architecture}}{8}}
\newlabel{fig:nehalemtime}{{11}{8}}
\newlabel{fig:hw10}{{12(a)}{9}}
\newlabel{sub@fig:hw10}{{(a)}{9}}
\newlabel{fig:hw5}{{12(b)}{9}}
\newlabel{sub@fig:hw5}{{(b)}{9}}
\newlabel{fig:hw10light}{{12(c)}{9}}
\newlabel{sub@fig:hw10light}{{(c)}{9}}
\newlabel{fig:hw5light}{{12(d)}{9}}
\newlabel{sub@fig:hw5light}{{(d)}{9}}
\@writefile{lof}{\contentsline {figure}{\numberline {12}{\ignorespaces Performance of Naive and pair-symmetric (P.S.) bilateral filtering kernel algorithms on GTX 280 NVidia card. X and Y represent the number of threads inside a block; number of blocks is listed next to the name of the algorithm (64x64 and 32x32).}}{9}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(a)}{\ignorespaces {Large 3000X3000 Image, Filter Width = $10$}}}{9}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(b)}{\ignorespaces {Large 3000X3000 Image, Filter Width = $5$}}}{9}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(c)}{\ignorespaces {Smaller 768X512 Image, Filter Width = $10$}}}{9}}
\@writefile{lof}{\contentsline {subfigure}{\numberline{(d)}{\ignorespaces {Smaller 768X512 Image, Filter Width = $5$}}}{9}}
\newlabel{fig:gpuresults}{{12}{9}}
\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {VI-B}}Performance of bilateral filtering kernel on GPU}{9}}
\bibstyle{IEEEtran}
\bibdata{paper}
\bibcite{Tomasi1998}{1}
\bibcite{zhang2008}{2}
\bibcite{eisemann2004}{3}
\bibcite{Bae2006}{4}
\bibcite{DeCarlo2002}{5}
\bibcite{Xiao2006}{6}
\bibcite{Ramanath2003}{7}
\bibcite{Paris2009}{8}
\bibcite{Pham2005}{9}
\bibcite{yang2009}{10}
\bibcite{xu2009}{11}
\bibcite{kdatta2008}{12}
\bibcite{matrix-multi}{13}
\bibcite{MatrixMultiFloating}{14}
\bibcite{NCCmatching}{15}
\@writefile{toc}{\contentsline {section}{\numberline {VII}Conclusion and future work}{10}}
\newlabel{sec:conclusion}{{VII}{10}}
\@writefile{toc}{\contentsline {section}{References}{10}}
